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NB4N121K 3.3V Differential In 1:21 Differential Fanout Clock Driver with HCSL level Output
http://onsemi.com Description
The NB4N121K is a Clock differential input fanout distribution 1 to 21 HCSL level differential outputs, optimized for ultra low propagation delay variation. The NB4N121K is designed with HCSL clock distribution for FBDIMM applications in mind. Inputs can accept differential LVPECL, CML, or LVDS levels. Single-ended LVPECL, CML, LVCMOS or LVTTL levels are accepted with the proper VREFAC supply (see Figures 5, 10, 11, 12, and 13). Clock input pins incorporate an internal 50 W on die termination resistors. Output drive current at IREF (Pin 1) for 1X load is selected by connecting to GND. To drive a 2X load, connect IREF to VCC. See Figure 9. The NB4N121K specifically guarantees low output-to-output skews. Optimal design, layout, and processing minimize skew within a device and from device to device. System designers can take advantage of the NB4N121K's performance to distribute low skew clocks across the backplane or the motherboard.
Features
QFN-52 MN SUFFIX CASE 485M
1 52
MARKING DIAGRAM*
52 1 NB4N 121K AWLYYWWG
* Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and * 340 ps Typical Rise and Fall Times * 800 ps Typical Propagation Delay * Dtpd 100 ps Maximum Propagation Delay Variation Per Each * * * *
Differential Pair <1 ps RMS Additive Clock jitter Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V Differential HCSL Output Level (700 mV Peak-to-Peak) Pb-Free Packages are Available* 400 MHz
A WL YY WW G
= Assembly Site = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional marking information, refer to Application Note AND8002/D.
Q0 VTCLK Q0 Q1 Q1 CLK CLK Q19 Q19 VTCLK VCC GND RREF IREF Q20 Q20
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Figure 1. Pin Configuration (Top View) ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2007
1
June, 2007 - Rev. 0
Publication Order Number: NB4N121K/D
NB4N121K
VCC
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Exposed Pad (EP)
52
51
50
49
48
47
46
45
44
43
42
41
40
IREF GND VTCLK CLK CLK VTCLK VCC Q20 Q20 Q19 Q19 Q18 Q18
1 2 3 4 5 6 7 8 9 10 11 12 13
39 38 37 36 35 34
VCC Q6 Q6 Q7 Q7 Q8 Q8 Q9 Q9 Q10 Q10 Q11 Q11
NB4N121K
33 32 31 30 29 28 27
14
15
16
17
18
19
20
21
22
23
24
25 Q12
Figure 2. Pinout Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin 1 Name IREF I/O Output Description Output current programming pin to select load drive. For 1X configuration, connect IREF to GND, or for 2X configuration, connect IREF to VCC (See Figure 9). Supply Ground. GND pin must be externally connected to power supply to guarantee proper operation. Internal 50 W Termination Resistor connection Pins. In the differential configuration when the input termination pins are connected to the com mon termination voltage, and if no signal is applied then the device may be susceptible to self-oscillation. CLOCK Input (TRUE) CLOCK Input (INVERT) Positive Supply pins. VCC pins must be externally connected to a power supply to guarantee proper operation. Output (INVERT)
2 3, 6
GND VTCLK, VTCLK
-
4 5 7, 26, 39, 52 8, 10, 12, 14, 16, 18, 20, 22, 24, 27, 29, 31, 33, 35, 37, 40, 42, 44, 46, 48, 50 9, 11, 13, 15, 17, 19, 21, 23, 25, 28, 30, 32, 34, 36, 38, 41, 43, 45, 47, 49, 51 Exposed Pad
CLK CLK VCC Q[20-0]
LVPECL Input LVPECL Input HCSL Output
Q[20-0]
HCSL Output
Output (TRUE)
EP
GND
Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a sufficient heat-sinking conduit for proper thermal operation. (Note 1)
1. The exposed pad must be connected to the circuit board ground.
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2
VCC
Q17
Q17
Q16
Q16
Q15
Q15
Q14
Q14
Q13
Q13
Q12
26
NB4N121K
Table 2. ATTRIBUTES
Characteristic Input Default State Resistors ESD Protection Moisture Sensitivity (Note 2) Flammability Rating Oxygen Index: 28 to 34 Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Human Body Model QFN-52 Value None >2 kV Level 3 UL 94 V-0 @ 0.125 in 622
Table 3. MAXIMUM RATINGS (Note 3)
Symbol VCC VI VINPP IOUT TA Tstg qJA qJC Tsol Parameter Positive Power Supply Positive Input Differential Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 3) Thermal Resistance (Junction-to-Case) Wave Solder Pb-Free 0 lfpm 500 lfpm 2S2P (Note 4) QFN-52 QFN-52 QFN-52 |CLK - CLKb| Continuous Surge QFN-52 Condition 1 GND = 0 V GND = 0 V Condition 2 Rating 6 GND - 0.3 v VI v VCC 1.2 50 100 -40 to +70 -65 to +150 25 19.6 21 265 Unit V V V mA mA C C C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard 51-6, multilayer board - 2S2P (2 signal, 2 power). 4. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB4N121K
Table 4. DC CHARACTERISTICS (VCC = 3.0 V to 3.6 V, TA = -40C to +70C Note 5)
Symbol IGND ICC IIH IIL Characteristic GND Supply Current (All Outputs Loaded) Power Supply Current (All Outputs Loaded) Input HIGH Current CLKx, CLKx Input LOW Current CLKx, CLKx -150 1X 2X Min 70 Typ 98 420 780 2.0 -2.0 150 Max 120 Unit mA mA mA mA
DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (Figures 5 and 7) Vth VIH VIL Input Threshold Reference Voltage Range (Note 6) Single-Ended Input HIGH Voltage Single-Ended Input LOW Voltage 1050 Vth + 150 GND VCC - 150 VCC Vth - 150 mV mV mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 6 and 8) VIHD VILD VID VCMR Differential Input HIGH Voltage Differential Input LOW Voltage Differential Input Voltage (VIHD - VILD) Input Common Mode Range 1200 GND 75 1163 VCC VCC - 75 2400 VCC - 75 mV mV mV
HCSL OUTPUTS (Figure 4) VOH VOL Output HIGH Voltage Output LOW Voltage 600 -150 740 0 900 150 mV mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input parameters vary 1:1 with VCC. Measurements taken with outputs in either 1X (all outputs loaded 50 W to GND) or 2X (all outputs loaded 25 W to GND) configuration, see Figure 9. For 1X configuration, connect IREF to GND, or for 2X configuration, connect IREF to VCC. 6. Vth is applied to the complementary input when operating in single ended mode.
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NB4N121K
Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; -40C to +70C (Note 7)
Symbol VOUTPP Characteristic Output Voltage Amplitude (@ VINPPmin) fin = 133 MHz fin = 166 MHz fin = 200 MHz CLK/CLK to Qx/Qx 550 Min Typ 725 725 725 800 Max 900 900 900 950 100 20 50 80 150 fin =133 MHz fin = 166 MHz fin = 200 MHz 150 250 1 Unit mV
tPLH, tPHL DtPLH, DtPHL tSKEW
Propagation Delay to (See Figure 3)
ps ps ps ps ps ps ps
Propagation Delay Variations Variation Per Each Diff Pair CLK/CLK to Qx/Qx (Note 8) (See Figure 3) Duty Cycle Skew (Note 9) Within-Device Skew, 1X Mode Only (Note 10) Within-Device Skew, 2X Mode (Note 10) Device-to-Device Skew (Note 10) RMS Random Clock Jitter (Note 11)
tJITTER
VINPP Vcross DVcross tr, tf Dtr, Dtf
Input Voltage Swing/Sensitivity (Differential Configuration) Absolute Crossing Magnitude Voltage Variation in Magnitude of Vcross Absolute Magnitude in Output Risetime and Falltime (From 175 mV to 525 mV) Variation in Magnitude of Risetime and Falltime (Single-Ended) (See Figure 4) Qx, Qx Qx, Qx 1X 2X
1200 550 150
mV mV mV ps ps
175
340
700
125 150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. Measurements taken with outputs in either 1X (all outputs loaded 50 W to GND) or 2X (all outputs loaded 25 W to GND) configuration, see Figure 9. For 1X configuration, connect IREF to GND, or for 2X configuration, connect IREF to VCC. Typical gain is 20 dB. 8. Measured from the input pair crosspoint to each single output pair crosspoint across temp and voltage ranges. 9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw- and Tpw+. 10. Skew is measured between outputs under identical transition @ 133 MHz. 11. Additive RMS jitter with 50% duty cycle clock signal using phase noise integrated from 12 KHz to 33 MHz CLK VINPP = VIH(CLK) - VIL(CLK) = VIH(CLK) - VIL(CLK) CLK tPLH Q VOUTPP = VOH(Q) - VOL(Q) = VOH(Q) - VOL(Q) Q tPHL
DtPLH
DtPHL
Figure 3. AC Reference Measurement
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NB4N121K
525 mV VCROSS 175 mV DVCROSS
tr
tf
Figure 4. HCSL Output Parameter Characteristics
CLK Vth
CLK
CLK Vth
CLK
Figure 5. Differential Input Driven Single-Ended (Vth = VREFAC)
Figure 6. Differential Inputs Driven Differentially
VCC Vthmax
VIHmax VILmax VIH Vth VIL VIHmin VILmin
VCC VCMmax
VIHDmax VILDmax VID = VIHD - VILD VIHDtyp VILDtyp
Vth
VCMR
Vthmin GND
VCMmin GND
VIHDmin VILDmin
Figure 7. Vth Diagram
Figure 8. VCMR Diagram
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NB4N121K
Qx RS1C Z0 = 50 W 1X Load
HCSL Driver RS2C Qx RREFA 2X Load Option A. For 1X configuration, connect IREF pin to GND or for 2X configuration, connect IREF pin to VCC. To adjust load drive for 1X configuration, use RREF from 0 W to 1 kW, to adjust 2X load, use 20 kW to 50 kW. B. RL1, RL2: 50 W for 1X Load 25 W for 2X Load C. RS1, RS2: 0 W for Test and Evaluation. Select to Minimizing Ringing. D. CL1, CL2, CL3, CL4: Receiver Input Simulation Load Capacitance Only Z0 = 50 W RL1B 50 RL2B 50 CL1D 2 pF CL2D 2 pF
Receiver
Receiver 2
CL3D 2 pF
CL4D 2 pF
Figure 9. Typical Termination Configuration for Output Driver and Device Evaluation CLx for Test Only (Representing Receiver Input Loading); Not Added to Application
VCC = 3.3 V
VCC = 3.3 V
VCC = 3.3 V
VCC = 3.3 V
Z0 = 50 W
NB4N121K D 50 W* LVDS Driver 50 W* D
Z0 = 50 W
NB4N121K D 50 W*
LVPECL Driver
VTD VTD Z0 = 50 W
VTD VTD Z0 = 50 W 50 W* D
VTD = VTD = VCC - 2.0 V GND GND GND
VTD = VTD GND
*RTIN, Internal Input Termination Resistor
*RTIN, Internal Input Termination Resistor
Figure 10. LVPECL Interface
Figure 11. LVDS Interface
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NB4N121K
VCC VCC VCC VCC
Z0 = 50 W VCC CML Driver VTD VTD Z0 = 50 W
NB4N121K D 50 W* LVCMOS/ LVTTL Driver
Z0 = 50 W
NB4N121K D 50 W*
VTD VTD 50 W* D 1.5 kW**
50 W* D
VTD = VTD = VCC GND GND GND GND VTD = OPEN D = GND *RTIN, Internal Input Termination Resistor *RTIN, Internal Input Termination Resistor **or VREFAC GND
Figure 12. Standard 50 W Load CML Interface
Figure 13. LVCMOS/LVTTL Interface
VCC
VDR
INTQ
INTQb
Q
Qb
Figure 14. HCSL Output Structure
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NB4N121K
ORDERING INFORMATION
Device NB4N121KMN NB4N121KMNG NB4N121KMNR2 NB4N121KMNR2G Package QFN-52 QFN-52 (Pb-Free) QFN-52 QFN-52 (Pb-Free) Shipping 260 Units / Tray 260 Units / Tray 2000 / Tape & Reel 2000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NB4N121K
PACKAGE DIMENSIONS
52 PIN QFN 8x8 CASE 485M-01 ISSUE A
D A B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.60 0.80 0.20 REF 0.18 0.30 8.00 BSC 6.50 6.80 8.00 BSC 6.50 6.80 0.50 BSC 0.20 --0.30 0.50
E
2X
0.15 C
2X
0.15 C A2 0.10 C A 0.08 C
SEATING PLANE
DIM A A1 A2 A3 b D D2 E E2 e K L
A1 D2
14 13
A3
REF
C
26 27
52 X
L E2
1 52 X
39 52 40
K
e
52 X
b
NOTE 3
0.10 C A B 0.05 C
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NB4N121K/D

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